Non-Volatile Latch Using Magneto-Electric and Ferro-Electric Tunnel Junctions
A non-volatile memory circuit includes an SRAM cell with magnetoelectric or ferroelectric structures for maintaining data within the SRAM cell even with power off in some implementations.
Two memory structures under development in the Nanoelectronics Research Initiative (NRI) of the Semiconductor Research Corporation (SRC) show promise for low power, small area, high performance non-volatile memory devices. However, these will not operate in conjunction with conventional CMOS directly. This invention describes circuit configurations that allow such interfacing.
Patent Link: US9368208
Patent Information:
| App Type |
Country |
Serial No. |
Patent No. |
Patent Status |
File Date |
Issued Date |
Expire Date |
|